S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 307

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

8.1.4
The S12XDBG module can be used in all MCU functional modes.
During BDM hardware accesses and whilst the BDM module is active, CPU12X monitoring is disabled.
Thus breakpoints, comparators, and CPU12X bus tracing are disabled but XGATE bus monitoring
accessing the S12XDBG registers, including comparator registers, is still possible. While in active BDM
or during hardware BDM accesses, XGATE activity can still be compared, traced and can be used to
generate a breakpoint to the XGATE module. When the CPU12X enters active BDM Mode through a
BACKGROUND command, with the S12XDBG module armed, the S12XDBG remains armed.
The S12XDBG module tracing is disabled if the MCU is secure. However, breakpoints can still be
generated if the MCU is secure.
Freescale Semiconductor
Enable
BDM
•
•
•
•
x
0
0
1
1
XGATE S/W breakpoint request trigger independent of comparators
TRIG Immediate software trigger independent of comparators
Four trace modes
— Normal: change of flow (COF) PC information is stored (see
— Loop1: same as Normal but inhibits consecutive duplicate source address entries
— Detail: address and data for all cycles except free cycles and opcode fetches are stored
— Pure PC: All program counter addresses are stored.
4-stage state sequencer for trace buffer control
— Tracing session trigger linked to Final State of state sequencer
— Begin, End, and Mid alignment of tracing to trigger
flow definition.
Modes of Operation
Active
BDM
x
0
1
0
1
Secure
MCU
1
0
0
0
0
Table 8-3. Mode Dependent Restriction Summary
MC9S12XE-Family Reference Manual Rev. 1.25
Matches Enabled
Comparator
XGATE only
Yes
Yes
Yes
Active BDM not possible when not enabled
Breakpoints
XGATE only
Only SWI
Possible
Yes
Yes
Chapter 8 S12X Debug (S12XDBGV3) Module
Section
XGATE only
Possible
Tagging
Yes
Yes
Yes
8.4.5.2.1) for change of
XGATE only
Possible
Tracing
Yes
Yes
No
307