S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 639

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
1. Read: Anytime when TXEx flag is set (see
16.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
“MSCAN Control Register 0
stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
1. Read: For transmit buffers: Anytime when TXEx flag is set (see
Freescale Semiconductor
Module Base + 0x00XD
Module Base + 0x00XE
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
Write: Anytime when TXEx flag is set (see
corresponding transmit buffer is selected in CANTBSEL (see
(CANTBSEL)”)
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
Buffer Selection Register
Write: Unimplemented
•
Reset:
Reset:
The transmission buffer with the lowest local priority field wins the prioritization.
W
W
R
R
Time Stamp Register (TSRH–TSRL)
TSR15
PRIO7
0
7
7
x
(CANTBSEL)”). For receive buffers: Anytime when RXF is set.
Figure 16-37. Time Stamp Register — High Byte (TSRH)
Figure 16-36. Transmit Buffer Priority Register (TBPR)
TSR14
PRIO6
6
0
6
x
(CANCTL0)”). In case of a transmission, the CPU can only read the time
MC9S12XE-Family Reference Manual Rev. 1.25
Section 16.3.2.7, “MSCAN Transmitter Flag Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
TSR13
PRIO5
0
5
5
x
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
TSR12
PRIO4
4
0
4
x
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Section 16.3.2.7, “MSCAN Transmitter Flag Register
TSR11
PRIO3
0
x
3
3
Section 16.3.2.11, “MSCAN Transmit
TSR10
PRIO2
2
0
2
x
(CANTFLG)”) and the
(CANTFLG)”) and the
Access: User read/write
Access: User read/write
PRIO1
TSR9
Section 16.3.2.1,
0
x
1
1
PRIO0
TSR8
0
0
0
x
639
(1)
(1)