S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 545

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

14.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
14.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Read: Anytime
Freescale Semiconductor
Module Base + 0x000E
Module Base + 0x000F
C[7:0]F
Reset
Reset
Field
7:0
Section 14.3.2.6, “Timer System Control Register 1
W
W
R
R
Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
TOF
C7F
0
0
7
7
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
= Unimplemented or Reserved
C6F
0
0
0
6
6
Figure 14-18. Main Timer Interrupt Flag 1 (TFLG1)
Figure 14-19. Main Timer Interrupt Flag 2 (TFLG2)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-17. TFLG1 Field Descriptions
C5F
0
0
0
5
5
(TSCR1)”.
C4F
NOTE
0
0
0
4
4
Description
(TSCR1)”).
C3F
0
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
C2F
0
0
0
2
2
C1F
0
0
0
1
1
C0F
0
0
0
0
0
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