S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 80

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 1 Device Overview MC9S12XE-Family
MPU is set, access to system resources is only allowed if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.4.4.2
This state is intended for carrying out system tasks and is entered by setting the U bit of the condition codes
register while in Supervisor state. Restrictions apply for the execution of several CPU instructions in User
state and access to system resources is only allowed in if enabled by a memory range descriptor as defined
in the Memory Protection Unit (MPU) description.
1.5
The MCU security feature allows the protection of the on chip Flash and emulated EEPROM memory. For
a detailed description of the security features refer to the S12X9SEC description.
1.6
Consult the S12XCPU manual and the S12XINT description for information on exception processing.
1.6.1
Resets are explained in detail in the Clock Reset Generator (CRG) description.
1.6.2
Table 1-14
(S12XINT) provides an interrupt vector base register (IVBR) to relocate the vectors. Associated with each
I-bit maskable service request is a configuration register. It selects if the service request is enabled, the
service request priority level and whether the service request is handled either by the S12X CPU or by the
XGATE module.
80
Vector Address
Security
Resets and Interrupts
lists all interrupt sources and vectors in the default order of priority. The interrupt module
Resets
Vectors
$FFFC
User State
$FFFE
$FFFE
$FFFE
$FFFE
$FFFA
Table 1-13. Reset Sources and Vector Locations
MC9S12XE-Family Reference Manual Rev. 1.25
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
COP watchdog reset
External pin RESET
Clock monitor reset
Reset Source
Mask
None
None
None
None
None
None
CCR
PLLCTL (CME, SCME)
COP rate select
Local Enable
None
None
None
None
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