S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 244

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 5 External Bus Interface (S12XEBIV4)
1. All inputs are capable of reducing input threshold level
2. Time-multiplex means that the respective signals share the same pin on chip level and are active alternating in a dedicated
3. Function-multiplex means that one of the respective signals sharing the same pin on chip level continuously uses the pin
244
RE
ADDR[22:20]
ACC[2:0]
ADDR[19:16]
IQSTAT[3:0]
ADDR[15:1]
IVD[15:1]
ADDR0
IVD0
UDS
LSTRB
LDS
RW
WE
CS[3:0]
DATA[15:8]
DATA[7:0]
EWAIT
time slot (in modes where applicable).
depending on configuration and reset state.
Signal
I
(1)
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
/O
(F)unction
EBI Signal
—
—
—
—
—
—
—
—
—
—
T
T
T
T
Multiplex
(T)ime
Table 5-2. External System Signals Associated with XEBI
(2)
—
—
—
—
—
—
—
—
—
—
—
F
F
F
(3)
MC9S12XE-Family Reference Manual Rev. 1.25
Read Enable, indicates external read access
Access source
Instruction Queue Status
Internal visibility read data
External address
Internal visibility read data
Upper Data Select, indicates external access
to the high byte DATA[15:8]
Low Strobe, indicates valid data on DATA[7:0]
Lower Data Select, indicates external access
to the low byte DATA[7:0]
Read/Write, indicates the direction of internal
data transfers
Write Enable, indicates external write access
External control for external bus access
stretches (adding wait states)
External address
External address
External address
Chip select
Bidirectional data (even address)
Bidirectional data (odd address)
Description
NS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
SS
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Available in Modes
Freescale Semiconductor
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
NX
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ES
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EX
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ST
No
No
No
No
No
No