S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 287

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

7.3.2.4
Register Global Address 0x7FFF08
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
7.3.3
The family ID is a 8-bit value located in the firmware ROM (at global address: 0x7FFF0F). The read-only
value is a unique family ID which is 0xC1 for S12X devices.
7.4
The BDM receives and executes commands from a host via a single wire serial interface. There are two
types of BDM commands: hardware and firmware commands.
Hardware commands are used to read and write target system memory locations and to enter active
background debug mode, see
includes all memory that is accessible by the CPU.
Firmware commands are used to read and write CPU resources and to exit from active background debug
mode, see
accumulator (D), X index register (X), Y index register (Y), stack pointer (SP), and program counter (PC).
Hardware commands can be executed at any time and in any mode excluding a few exceptions as
highlighted (see
“Security”). Firmware commands can only be executed when the system is not secure and is in active
background debug mode (BDM).
Freescale Semiconductor
BGP[6:0]
Reset
BGAE
Field
6–0
7
W
R
Functional Description
Section 7.4.4, “Standard BDM Firmware
BGAE
Family ID Assignment
BDM Global Page Access Enable Bit — BGAE enables global page access for BDM hardware and firmware
read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD_ and
WRITE_BD_) can not be used for global accesses even if the BGAE bit is set.
0 BDM Global Access disabled
1 BDM Global Access enabled
BDM Global Page Index Bits 6–0 — These bits define the extended address bits from 22 to 16. For more
detailed information regarding the global page window scheme, please refer to the S12X_MMC Block Guide.
BDM Global Page Index Register (BDMGPR)
7
0
Section 7.4.3, “BDM Hardware
BGP6
6
0
Figure 7-6. BDM Global Page Register (BDMGPR)
Section 7.4.3, “BDM Hardware
MC9S12XE-Family Reference Manual Rev. 1.25
Table 7-5. BDMGPR Field Descriptions
BGP5
5
0
BGP4
Commands”) and in secure mode (see
4
0
Commands”. The CPU resources referred to are the
Description
BGP3
Commands”. Target system memory
3
0
Chapter 7 Background Debug Module (S12XBDMV2)
BGP2
2
0
BGP1
1
0
Section 7.4.1,
BGP0
0
0
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