S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 664

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
17.3.0.1
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
17.3.0.2
Read: Anytime
Write: Anytime
664
Module Base + 0x0000
Module Base + 0x0001
PFLMT[1:0]
PITSWAI
PITFRZ
Reset
Reset
Field
PITE
1:0
7
6
5
W
W
R
R
PFLT7
PITE
PIT Module Enable Bit — This bit enables the PIT module. If PITE is cleared, the PIT module is disabled and
flag bits in the PITTF register are cleared. When PITE is set, individually enabled timers (PCE set) start down-
counting with the corresponding load register values.
0 PIT disabled (lower power consumption).
1 PIT is enabled.
PIT Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 PIT operates normally in wait mode
1 PIT clock generation stops and freezes the PIT module when in wait mode
PIT Counter Freeze while in Freeze Mode Bit — When during debugging a breakpoint (freeze mode) is
encountered it is useful in many cases to freeze the PIT counters to avoid e.g. interrupt generation. The PITFRZ
bit controls the PIT operation while in freeze mode.
0 PIT operates normally in freeze mode
1 PIT counters are stalled when in freeze mode
PIT Force Load Bits for Micro Timer 1:0 — These bits have only an effect if the corresponding micro timer is
active and if the PIT module is enabled (PITE set). Writing a one into a PFLMT bit loads the corresponding 8-bit
micro timer load register into the 8-bit micro timer down-counter. Writing a zero has no effect. Reading these bits
will always return zero.
Note: A micro timer force load affects all timer channels that use the corresponding micro time base.
PIT Control and Force Load Micro Timer Register (PITCFLMT)
PIT Force Load Timer Register (PITFLT)
0
0
0
7
7
Figure 17-3. PIT Control and Force Load Micro Timer Register (PITCFLMT)
= Unimplemented or Reserved
PITSWAI
PFLT6
0
0
0
6
6
Figure 17-4. PIT Force Load Timer Register (PITFLT)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 17-2. PITCFLMT Field Descriptions
PITFRZ
PFLT5
0
0
0
5
5
PFLT4
0
0
0
0
4
4
Description
PFLT3
0
0
0
0
3
3
PFLT2
0
0
0
0
2
2
PFLMT1
Freescale Semiconductor
PFLT1
0
0
0
0
1
1
PFLMT0
PFLT0
0
0
0
0
0
0