S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 772

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 21 Serial Peripheral Interface (S12SPIV5)
21.3.2.5
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
772
Module Base +0x0004
Module Base +0x0005
Reset
Reset
W
W
R
R
The SPI data register is both the input and output register for SPI data. A write to this register
allows data to be queued and transmitted. For an SPI configured as a master, queued data is
transmitted immediately after the previous transmission has completed. The SPI transmitter empty
flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift
register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data
is kept as valid data in the receive shift register until the start of another transmission. The data in
the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF
remains set (see
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a
third transmission, the data in the receive shift register has become invalid and is not transferred
into the SPIDR (see
R15
T15
R7
T7
SPI Data Register (SPIDR = SPIDRH:SPIDRL)
0
0
7
7
Figure
R14
T14
R6
T6
0
0
6
6
Figure
Figure 21-7. SPI Data Register High (SPIDRH)
Figure 21-8. SPI Data Register Low (SPIDRL)
21-9).
MC9S12XE-Family Reference Manual Rev. 1.25
21-10).
R13
T13
R5
T5
0
0
5
5
R12
T12
R4
T4
0
0
4
4
R11
T11
R3
T3
0
0
3
3
R10
T10
R2
T2
0
0
2
2
Freescale Semiconductor
R9
R1
T9
T1
0
0
1
1
R8
R0
T8
T0
0
0
0
0