S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 701

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

19.3.2.5
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 19.4.2.5, “Left Aligned Outputs”
detailed description of the PWM output modes.
Read: Anytime
Write: Anytime
19.3.2.6
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
Freescale Semiconductor
Module Base + 0x0004
Module Base + 0x0005
CAE[7:0]
Reset
Reset
Field
7–0
W
W
R
R
CON67
CAE7
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
PWM Center Align Enable Register (PWMCAE)
PWM Control Register (PWMCTL)
0
0
7
7
Write these bits only when the corresponding channel is disabled.
= Unimplemented or Reserved
CON45
Figure 19-7. PWM Center Align Enable Register (PWMCAE)
CAE6
0
0
6
6
Figure 19-8. PWM Control Register (PWMCTL)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 19-8. PWMCAE Field Descriptions
CON23
CAE5
0
0
5
5
and
Section 19.4.2.6, “Center Aligned Outputs”
CON01
CAE4
NOTE
0
0
4
4
Description
PSWAI
CAE3
0
0
3
3
Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
CAE2
PFRZ
0
0
2
2
CAE1
0
0
0
1
1
for a more
CAE0
0
0
0
0
0
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