S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 538

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Read: Anytime
Write: Writable in special modes.
All bits reset to zero.
14.3.2.6
Read or write: Anytime except PRNT bit is write once
All bits reset to zero.
538
Module Base + 0x0005
Module Base + 0x0006
TCNT[15:0]
Reset
Reset
TSWAI
Field
Field
15:0
TEN
7
6
W
W
R
R
TCNT7
Timer Counter Bits — The 16-bit main timer is an up counter. A read to this register will return the current value
of the counter.
Note: A separate read/write for high byte and low byte in test mode will give a different result than accessing
TEN
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
Note: If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the ÷64 is
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer counter, pulse accumulators and modulus down counter when the MCU is in wait mode.
Timer System Control Register 1 (TSCR1)
0
0
7
7
Timer interrupts cannot be used to get the MCU out of wait.
them as a word. The period of the first count after a write to the TCNT registers may be a different size
because the write is not synchronized with the prescaler clock.
generated by the timer prescaler.
= Unimplemented or Reserved
TCNT6
TSWAI
Figure 14-9. Timer System Control Register 1 (TSCR1)
0
0
6
6
Access to the counter register will take place in one clock cycle.
Figure 14-8. Timer Count Register Low (TCNT)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-7. TSCR1 Field Descriptions
Table 14-6. TCNT Field Descriptions
TCNT5
TSFRZ
0
0
5
5
TCNT4
TFFCA
0
0
4
4
Description
Description
TCNT3
PRNT
0
0
3
3
TCNT2
0
0
0
2
2
TCNT1
Freescale Semiconductor
0
0
0
1
1
TCNT0
0
0
0
0
0