S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 633

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Read:
Write:
Reset: Undefined because of RAM-based implementation
16.3.3.1
The identifier registers for an extended format identifier consist of a total of 32 bits: ID[28:0], SRR, IDE,
and RTR. The identifier registers for a standard format identifier consist of a total of 13 bits: ID[10:0],
RTR, and IDE.
Freescale Semiconductor
Register
Register
0x00X0
0x00X1
0x00X2
0x00X3
Name
Name
IDR0
IDR1
IDR2
IDR3
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
For receive buffers, only when RXF flag is set (see
Register
For transmit buffers, anytime when TXEx flag is set (see
Flag Register
Section 16.3.2.11, “MSCAN Transmit Buffer Selection Register
Unimplemented for receive buffers.
Figure 16-24. Receive/Transmit Message Buffer — Extended Identifier Mapping (continued)
Identifier Registers (IDR0–IDR3)
Figure 16-25. Receive/Transmit Message Buffer — Standard Identifier Mapping
W
W
W
W
R
R
R
R
(CANRFLG)”).
Bit 7
Bit 7
ID10
ID2
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
= Unused, always read ‘x’
= Unused, always read ‘x’
MC9S12XE-Family Reference Manual Rev. 1.25
ID9
ID1
6
6
ID8
ID0
5
5
Chapter 16 Freescale’s Scalable Controller Area Network (S12MSCANV3)
RTR
ID7
4
4
Section 16.3.2.5, “MSCAN Receiver Flag
IDE (=0)
Section 16.3.2.7, “MSCAN Transmitter
Section 16.3.2.7, “MSCAN Transmitter
ID6
3
3
(CANTBSEL)”).
(CANTBSEL)”).
ID5
2
2
ID4
1
1
Bit 0
Bit0
ID3
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