S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 495

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

11.5.1
The reset sequence is initiated by any of the following events:
Upon detection of any reset event, an internal circuit drives the RESET pin low for 128 SYSCLK cycles
(see
However, the internal reset circuit of the S12XECRG cannot sequence out of current reset condition
without a running SYSCLK. The number of 128 SYSCLK cycles might be increased by n = 3 to 6
additional SYSCLK cycles depending on the internal synchronization latency. After 128+n SYSCLK
cycles the RESET pin is released. The reset generator of the S12XECRG waits for additional 64 SYSCLK
cycles and then samples the RESET pin to determine the originating source.
vector will be fetched.
Freescale Semiconductor
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Figure
Low level is detected at the RESET pin (External Reset).
Power on is detected.
Low voltage is detected.
Illegal Address Reset is detected (refer to device MMC information for details).
COP watchdog times out.
Clock monitor failure is detected and Self-Clock Mode was disabled (SCME=0).
(64 cycles after release)
11-21). Since entry into reset is asynchronous it does not require a running SYSCLK.
Description of Reset Operation
Sampled RESET Pin
External circuitry connected to the RESET pin should be able to raise the
signal to a valid logic one within 64 SYSCLK cycles after the low drive is
released by the MCU. If this requirement is not adhered to the reset source
will always be recognized as “External Reset” even if the reset was initially
caused by an other reset source.
1
1
1
0
COP Watchdog Reset
Reset Source
MC9S12XE-Family Reference Manual Rev. 1.25
Reset Pending
Clock Monitor
Table 11-17. Reset Vector Selection
Table 11-16. Reset Summary
X
0
1
0
Reset Pending
NOTE
COP
X
X
0
1
Chapter 11 S12XE Clocks and Reset Generator (S12XECRGV1)
COPCTL (CR[2:0] nonzero)
Illegal Address Reset/ External Reset
Local Enable
with rise of RESET pin
Illegal Address Reset/
Clock Monitor Reset
External Reset
Vector Fetch
POR / LVR /
POR / LVR /
COP Reset
Table 11-17
shows which
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