S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 400

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Chapter 10 XGATE (S12XGATEV3)
BFEXT
Operation
RS1[(o+w):o] ⇒ RD[w:0]; 0 ⇒ RD[15:(w+1)]
Extracts w+1 bits from register RS1 starting at position o and writes them right aligned into register RD.
The remaining bits in RD will be cleared. If (o+w) > 15 only bits [15:o] get extracted.
CCR Effects
Code and CPU Cycles
400
N:
Z:
V:
C:
BFEXT RD, RS1, RS2
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
C
15
15
15
MC9S12XE-Family Reference Manual Rev. 1.25
Address
Mode
TRI
0
Bit Field Extract
0
7
1
1
W4
0
5
W4=3, O4=2
0
4
3
3
Machine Code
RD
2
O4
Bit Field Extract
RS1
0
0
0
RS2
RS1
RD
BFEXT
RS2
Freescale Semiconductor
1
1
Cycles
P

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