S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 669

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Read: Anytime
Write: Anytime
17.3.0.9
Freescale Semiconductor
Module Base + 0x0024, 0x0025
Module Base + 0x000A, 0x000B
Module Base + 0x000E, 0x000F
Module Base + 0x0012, 0x0013
Reset
Reset
Reset
Reset
PLD[15:0]
W
Field
W
W
W
15:0
R
R PCNT
R PCNT
R PCNT
PLD15 PLD14 PLD13 PLD12 PLD11 PLD10 PLD9 PLD8 PLD7 PLD6 PLD5 PLD4 PLD3 PLD2 PLD1 PLD0
15
15
15
15
15
15
15
0
0
0
0
PIT Load Bits 15:0 — These bits set the 16-bit modulus down-counter load value. Writing a new value into the
PITLD register must be a 16-bit access, to ensure data consistency. It will not restart the timer. When the timer
has counted down to zero the PTF time-out flag will be set and the register value will be loaded. The PFLT bits
in the PITFLT register can be used to immediately update the count register with the new value if an immediate
load is desired.
PIT Count Register 0 to 7 (PITCNT0–7)
PCNT
PCNT
PCNT
14
14
14
14
14
14
14
0
0
0
0
PCNT
PCNT
PCNT
13
13
13
13
13
13
13
0
0
0
0
PCNT
PCNT
PCNT
12
12
12
12
12
12
12
0
0
0
0
Figure 17-19. PIT Count Register 0 (PITCNT0)
Figure 17-20. PIT Count Register 1 (PITCNT1)
Figure 17-21. PIT Count Register 2 (PITCNT2)
Figure 17-18. PIT Load Register 7 (PITLD7)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 17-9. PITLD0–7 Field Descriptions
PCNT
PCNT
PCNT
11
11
11
11
11
11
11
0
0
0
0
PCNT
PCNT
PCNT
10
10
10
10
10
10
10
0
0
0
0
PCN
PCN
PCN
T9
T9
T9
0
0
0
0
9
9
9
9
Description
PCN
PCN
PCN
T8
T8
T8
0
0
0
0
8
8
8
8
PCN
PCN
PCN
T7
T7
T7
0
0
0
0
7
7
7
7
Chapter 17 Periodic Interrupt Timer (S12PIT24B8CV2)
PCN
PCN
PCN
T6
T6
T6
0
0
0
0
6
6
6
6
PCN
PCN
PCN
T5
T5
T5
0
0
0
0
5
5
5
5
PCN
PCN
PCN
T4
T4
T4
0
0
0
0
4
4
4
4
PCN
PCN
PCN
T3
T3
T3
3
0
3
0
3
0
3
0
PCN
PCN
PCN
T2
T2
T2
0
0
0
0
2
2
2
2
PCN
PCN
PCN
T1
T1
T1
0
0
0
0
1
1
1
1
PCN
PCN
PCN
T0
T0
T0
0
0
0
0
0
0
0
0
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