S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 113

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source
2. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated
2.3.11
Freescale Semiconductor
Function
Address 0x0008 (PRR)
is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
pin values.
Altern.
Field
Reset
7-2
PE
PE
PE
1
0
W
R
Port E general purpose input/output data—Data Register
Port E bits 7 through 0 are associated with external bus control signals and interrupt inputs. These include mode
select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI, TAGLO),
Read/Write (RW), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS).
When not used with the alternative functions, Port E pins 7-2 can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
Port E general purpose input data and interrupt—Data Register, IRQ input.
This pin can be used as general purpose and IRQ input.
Port E general purpose input data and interrupt—Data Register, XIRQ input.
This pin can be used as general purpose and XIRQ input.
ECLKX2
XCLKS
Port E Data Register (PORTE)
PE7
or
0
7
= Unimplemented or Reserved
TAGHI
MODB
PE6
or
0
6
Table 2-12. PORTE Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 2-9. Port E Data Register (PORTE)
TAGLO
MODA
PE5
RE
or
or
0
5
ECLK
PE4
0
4
Description
EROMCTL
LSTRB
PE3
LDS
or
or
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PE2
RW
WE
or
0
2
Access: User read/write
—
PE1
IRQ
1
(2)
XIRQ
PE0
—
0
2
113
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