S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 513

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Freescale Semiconductor
S8C, S4C,
S2C, S1C
FRZ[1:0]
Field
FIFO
6–3
1–0
2
Conversion Sequence Length — These bits control the number of conversions per sequence.
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may or may not be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC12B16C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
V
RH
V
Input Signal
5.120 Volts
RL
= 5.12 Volts
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.003
0.002
0.000
= 0 Volts
...
Table 13-9. ATDCTL3 Field Descriptions (continued)
Table 13-10. Examples of ideal decimal ATD Results
MC9S12XE-Family Reference Manual Rev. 1.25
Table
(resolution=20mV)
13-12. Leakage onto the storage node and comparator reference capacitors
Codes
8-Bit
255
...
1
1
1
1
1
1
1
0
0
0
0
0
0
Description
(resolution=5mV)
Codes
10-Bit
1023
Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
...
4
4
4
3
3
2
2
2
1
1
0
0
0
(resolution=1.25mV)
(transfer curve has
1.25mV offset)
Codes
12-Bit
4095
17
16
14
12
11
...
9
8
6
4
3
2
1
0
Table 13-11
513