S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 311

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Freescale Semiconductor
DBGBRK
XGSBPE
COMRV
Field
BDM
3–2
1–0
5
4
XGATE S/W Breakpoint Enable — The XGSBPE bit controls whether an XGATE S/W breakpoint request is
passed to the CPU12X. The XGATE S/W breakpoint request is handled by the S12XDBG module, which can
request an CPU12X breakpoint depending on the state of this bit.
0 XGATE S/W breakpoint request is disabled
1 XGATE S/W breakpoint request is enabled
Background Debug Mode Enable — This bit determines if an S12X breakpoint causes the system to enter
Background Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled
by the ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12XDBG Breakpoint Enable Bits — The DBGBRK bits control whether the debugger will request a breakpoint
to either CPU12X or XGATE or both upon reaching the state sequencer Final State. If tracing is enabled, the
breakpoint is generated on completion of the tracing session. If tracing is not enabled, the breakpoint is
generated immediately. Please refer to
independent of the DBGBRK bits. XGATE software breakpoints force a breakpoint to the CPU12X independent
of the DBGBRK bit field configuration. See
Comparator Register Visibility Bits — These bits determine which bank of comparator register is visible in the
8-byte window of the S12XDBG module address map, located between 0x0028 to 0x002F. Furthermore these
bits determine which register is visible at the address 0x0027. See
DBGBRK
COMRV
00
01
10
11
00
01
10
11
Table 8-5. DBGC1 Field Descriptions (continued)
No breakpoint generated
XGATE breakpoint generated
CPU12X breakpoint generated
Breakpoints generated for CPU12X and XGATE
MC9S12XE-Family Reference Manual Rev. 1.25
Visible Comparator
Comparator A
Comparator B
Comparator C
Comparator D
Table 8-6. DBGBRK Encoding
Table 8-7. COMRV Encoding
Section 8.4.7
Resource Halted by Breakpoint
Table
8-6.
Description
for further details. XGATE software breakpoints are
Visible Register at 0x0027
Table
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
Chapter 8 S12X Debug (S12XDBGV3) Module
8-7.
311