S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 132

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
1. Read: Anytime.
Chapter 2 Port Integration Module (S12XEPIMV1)
2.3.39
132
Address 0x0252
Write:Never, writes to this register have no effect.
Write: Anytime.
DDRM
DDRM
DDRM
Field
PTIM
Field
Reset
7-0
7
6
5
W
R
Port M input data—
This register always reads back the buffered state of the associated pins. This can also be used to detect overload
or short circuit conditions on output pins.
Port M data direction—
This register controls the data direction of pin 7.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an output. In those cases the data
direction bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated
peripheral module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 6.
The enabled CAN3, routed CAN4, or routed SCI3 forces the I/O state to be an input. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port M data direction—
This register controls the data direction of pin 5.
The enabled CAN2, routed CAN0, or routed CAN4 forces the I/O state to be an output. Depending on the
configuration of the enabled routed SPI0 this pin will be forced to be input or output. In those cases the data direction
bits will not change. The DDRM bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
DDRM7
Port M Data Direction Register (DDRM)
0
7
DDRM6
0
6
Figure 2-37. Port M Data Direction Register (DDRM)
Table 2-35. DDRM Register Field Descriptions
Table 2-34. PTIM Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
DDRM5
0
5
DDRM4
0
4
Description
Description
DDRM3
3
0
DDRM2
0
2
Access: User read/write
Freescale Semiconductor
DDRM1
0
1
DDRM0
0
0
(1)