S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 554

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.3.2.20 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
Read: Anytime
Write only used in the flag clearing mechanism for bit 7. Writing a one to bit 7 clears the flag. Writing a
zero will not affect the current status of the bit.
554
Module Base + 0x0027
MCPR[1:0]
Reset
MCEN
ICLAT
FLMC
Field
1:0
4
3
2
W
R
MCZF
Input Capture Force Latch Action — When input capture latch mode is enabled (LATQ and BUFEN bit in
ICSYS are set), a write one to this bit immediately forces the contents of the input capture registers TC0 to TC3
and their corresponding 8-bit pulse accumulators to be latched into the associated holding registers. The pulse
accumulators will be automatically cleared when the latch action occurs.
Writing zero to this bit has no effect. Read of this bit will always return zero.
Force Load Register into the Modulus Counter Count Register — This bit is active only when the modulus
down-counter is enabled (MCEN = 1).
A write one into this bit loads the load register into the modulus counter count register (MCCNT). This also resets
the modulus counter prescaler.
Write zero to this bit has no effect. Read of this bit will return always zero.
Modulus Down-Counter Enable
0 Modulus counter disabled. The modulus counter (MCCNT) is preset to 0xFFFF. This will prevent an early
1 Modulus counter is enabled.
Modulus Counter Prescaler Select — These two bits specify the division rate of the modulus counter prescaler
when PRNT of TSCR1 is set to 0. The newly selected prescaler division rate will not be effective until a load of
the load register into the modulus counter count register occurs.
0
7
interrupt flag when the modulus down-counter is enabled.
Figure 14-43. 16-Bit Modulus Down-Counter FLAG Register (MCFLG)
= Unimplemented or Reserved
0
0
6
MCPR1
Table 14-23. MCCTL Field Descriptions (continued)
0
0
1
1
Table 14-24. Modulus Counter Prescaler Select
MC9S12XE-Family Reference Manual Rev. 1.25
0
0
5
MCPR0
0
1
0
1
0
0
4
Description
Prescaler Division
POLF3
0
3
16
1
4
8
POLF2
0
2
POLF1
Freescale Semiconductor
0
1
POLF0
0
0