S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 297

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

compared to the serial communication rate. This protocol allows a great flexibility for the POD designers,
since it does not rely on any accurate time measurement or short response time to any event in the serial
communication.
Figure 7-12
instruction is used as an example. First, the 8-bit instruction opcode is sent by the host, followed by the
address of the memory location to be read. The target BDM decodes the instruction. A bus cycle is grabbed
(free or stolen) by the BDM and it executes the READ_BYTE operation. Having retrieved the data, the
BDM issues an ACK pulse to the host controller, indicating that the addressed byte is ready to be retrieved.
After detecting the ACK pulse, the host initiates the byte retrieval process. Note that data is sent in the form
of a word and the host needs to determine which is the appropriate byte based on whether the address was
odd or even.
Freescale Semiconductor
BKGD Pin
(Target MCU)
ACK Pulse
BDM Clock
BKGD Pin
Transmits
Last Command Bit
16th Tick of the
Target
shows the ACK handshake protocol in a command level timing diagram. The READ_BYTE
READ_BYTE
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters wait or stop prior to executing a
hardware command, the ACK pulse will not be issued meaning that the
BDM command was not executed. After entering wait or stop mode, the
BDM command is no longer pending.
Host
Figure 7-12. Handshake Protocol at Command Level
High-Impedance
Byte Address
Target
32 Cycles
Figure 7-11. Target Acknowledge Pulse (ACK)
MC9S12XE-Family Reference Manual Rev. 1.25
BDM Decodes
the Command
Minimum Delay
From the BDM Command
NOTE
16 Cycles
BDM Executes the
READ_BYTE Command
Speedup Pulse
Chapter 7 Background Debug Module (S12XBDMV2)
Target
BDM Issues the
ACK Pulse (out of scale)
(2) Bytes are
Retrieved
Host
Next Bit
Earliest
Start of
High-Impedance
Host
Command
New BDM
Target
297