S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 1233

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
The number of program/erase cycles for the EEPROM/D-Flash depends upon the partitioning of D-Flash
used for EEPROM Emulation. Defining RAM size allocated for EEE as EEE-RAM and D-Flash partition
allocated to EEE as EEE_NVM, the minimum number of program/erase cycles is specified depending
upon the ratio of EEE_NVM/EEE_RAM. The minimum ratio EEE_NVM/EEE_RAM =8.
Freescale Semiconductor
5. This represents the number of writes of updated data words to the EEE_RAM partition. Typical endurance performance for
6. This is equivalent to using a single byte or aligned word in the EEE_RAM with 32K D-Flash allocated for EEEPROM
# K Cycles
(Log)
1,000,000
the Emulated EEPROM array is based on typical endurance performance and the EEE algorithm implemented on this
product family. Spec. table quotes typical endurance evaluated at 25°C for this product family.
100,000
10,000
1,000
100
10
10
Figure A-2. Program/Erase Dependency on D-Flash Partitioning
100
MC9S12XE-Family Reference Manual Rev. 1.25
1000
10,000
100,000
EEE_NVM/EEE_RAM ratio
(Log)
Appendix A Electrical Characteristics
20% Spec Cycles
10 Year Data Retention
Spec Cycles
5 Year Data Retention
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