S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 461

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

10.8.6
Table 10-24
Freescale Semiconductor
Return to Scheduler and Others
Semaphore Instructions
Single Register Instructions
Special Move instructions
Shift instructions Dyadic
Shift instructions immediate
Logical Triadic
Arithmetic Triadic
BRK
NOP
RTS
SIF
CSEM IMM3
CSEM RS
SSEM IMM3
SSEM RS
SEX RD
PAR RD
JAL RD
SIF RS
TFR RD,CCR
TFR CCR,RS
TFR RD,PC
BFFO RD, RS
ASR RD, RS
CSL RD, RS
CSR RD, RS
LSL RD, RS
LSR RD, RS
ROL RD, RS
ROR RD, RS
ASR RD, #IMM4
CSL RD, #IMM4
CSR RD, #IMM4
LSL RD, #IMM4
LSR RD, #IMM4
ROL RD, #IMM4
ROR RD, #IMM4
AND RD, RS1, RS2
OR RD, RS1, RS2
XNOR RD, RS1, RS2
SUB RD, RS1, RS2
SBC RD, RS1, RS2
ADD RD, RS1, RS2
ADC RD, RS1, RS2
Instruction Coding
summarizes all XGATE instructions in the order of their machine coding.
Functionality
Table 10-24. Instruction Set Summary (Sheet 1 of 3)
MC9S12XE-Family Reference Manual Rev. 1.25
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
10
0
0
0
0
IMM3
IMM3
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RS
RS
RS
RS
9
0
0
1
1
For compare use SUB R0,Rs1,Rs2
8
0
1
0
1
7
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS
RS
RS
RS
RS
RS
RS
RS
6
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
Chapter 10 XGATE (S12XGATEV3)
5
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RS2
RS2
RS2
RS2
RS2
RS2
RS2
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
461
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1