SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 930

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

40.8
930
Conversion Results
SAM9M10
When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and
stored in the
“TSADCC Last Converted Data
The channel EOC bit and the bit DRDY in the
PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and
DRDY can trigger an interrupt.
Reading one of the
sponding EOC bit.
Reading
sponding to the last converted channel.
Figure 40-5. EOCx and DRDY Flag Behavior
If the
converted, the corresponding Overrun Error (OVRE) flag is set in the
Register”.
In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun
Error) in the
The OVRE and GOVRE flags are automatically cleared when the
read.
“TSADCC Channel Data Register x (x = 0..7)”
(ADC_CHSR)
“TSADCC Last Converted Data Register”
(ADC_SR)
(ADC_SR)
EOCx
DRDY
“TSADCC Status
“TSADCC Channel Data Register x (x = 0..7)”
CHx
Write the ADC_CR
with START = 1
“TSADCC Channel Data Register x (x = 0..7)”
SHTIM
Conversion
Register”.
Time
Register”.
Read the ADC_CDRx
“TSADCC Status Register”
clears the DRDY bit and the EOC bit corre-
is not read before further incoming data is
Write the ADC_CR
with START = 1
of the current channel and in the
SHTIM
“TSADCC Status
Conversion
registers clears the corre-
Time
Read the ADC_LCDR
are both set. If the
6355D–ATARM–7-Sep-11
“TSADCC Status
Register”is