SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 19

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SAM9M10

Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9M10

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
7. System Controller
6355D–ATARM–7-Sep-11
A[25:0], controlled by 4 registers, DELAY5, DELAY6, DELAY7and DELAY8, located in the
HSMC3 user interface
A25 on PC[12] and A[24:19] on PC[7:2]
The delay can only be inserted on the HSMCI0 and HSMCI1 I/O lines, so on PA[9:2] and
PA[30:23]. The delay is controlled by 2 registers, DELAY1 and DELAY2, located in the PIOA
user interface.
The System Controller is a set of peripherals that allows handling of key elements of the system,
such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface also embeds the registers that configure the Matrix and a
set of registers for the chip configuration. The chip configuration registers configure the EBI chip
select assignment and voltage range for external memories.
• PIOA User interface
– D[31] <=> DELAY4[31:28]
– A[0] <=> DELAY5[3:0],
– A[1] <=> DELAY5[7:4],...,
– A[6] <=> DELAY5[27:24],
– A[7] <=> DELAY5[31:28]
– A[8] <=> DELAY6[3:0],
– A[9] <=> DELAY6[7:4],...,
– A[14] <=> DELAY6[27:24],
– A[15] <=> DELAY6[31:28]
– A[16] <=> DELAY7[3:0],
– A[17] <=> DELAY7[7:4],
– A[18] <=> DELAY7[11:8]
– A19 <=> DELAY7[15:12],
– A20 <=> DELAY7[19:16],...,
– A23 <=> DELAY7[31:28],
– A24 <=> DELAY8[3:0],
– A25 <=> DELAY8[7:4]
– PA[2] <=> DELAY1[3:0],
– PA[3] <=> DELAY1[7:4],...,
– PA[8] <=> DELAY1[27:24],
– PA[9] <=> DELAY1[31:28]
– PA[23] <=> DELAY2[3:0],
– PA[24] <=> DELAY2[7:4],...,
– PA[29] <=> DELAY2[27:24],
– PA[30] <=> DELAY2[31:28]
SAM9M10
19

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