SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1390

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

iv
SAM9M10
21 Static Memory Controller (SMC) ......................................................... 185
22 DDR/SDR SDRAM Controller (DDRSDRC) ......................................... 229
23 Error Corrected Code Controller (ECC) ............................................. 279
20.2
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
21.13
21.14
21.15
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
23.1
23.2
23.3
23.4
23.5
23.6
23.7
External Bus Interface (EBI) ..........................................................................160
Description .....................................................................................................185
I/O Lines Description .....................................................................................185
Multiplexed Signals ........................................................................................185
Application Example ......................................................................................186
Product Dependencies ..................................................................................186
External Memory Mapping .............................................................................187
Connection to External Devices ....................................................................187
Standard Read and Write Protocols ..............................................................192
Automatic Wait States ...................................................................................200
Data Float Wait States ...................................................................................205
External Wait .................................................................................................209
Slow Clock Mode ...........................................................................................215
Asynchronous Page Mode ............................................................................218
Programmable IO Delays ..............................................................................221
Static Memory Controller (SMC) User Interface ............................................222
Description .....................................................................................................229
Embedded Characteristics ............................................................................229
DDRSDRC Module Diagram .........................................................................231
Initialization Sequence ...................................................................................232
Functional Description ...................................................................................237
Software Interface/SDRAM Organization, Address Mapping ........................256
Programmable IO Delays ..............................................................................258
DDR SDR SDRAM Controller (DDRSDRC) User Interface ...........................259
Description .....................................................................................................279
Block Diagram ...............................................................................................279
Functional Description ...................................................................................279
Error Corrected Code Controller (ECC) User Interface .................................284
Registers for 1 ECC for a page of 512/1024/2048/4096 bytes ......................295
Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes,
bit word 297
Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes,
bit word 305
6355D–ATARM–7-Sep-11
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