SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 134

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 19-3.
Table 19-4.
19.3
134
5
6
7
1
2
3
4
5
6
7
0
Internal Periph.
Internal SRAM 0
Memory Mapping
DDR Port 3
Master
Internal Periph.
Slave
LCD User Int.
UDPHS RAM
Internal ROM
SAM9M10
DDR Port 0
DDR Port 1
DDR Port 2
DDR Port 3
UHP OHCI
UHP EHCI
EBI
VDEC
EBI
SAM9M10 Masters to Slaves Access with VDEC_SEL = 0 (Continued)
SAM9M10 Masters to Slaves Access with VDEC_SEL = 1 (default)
ARM
Instr.
X
X
-
926
.
Table 19-5
the Remap status (RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and
the BMS state at reset.
Table 19-5.
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each
AHB master several memory mappings. In fact, depending on the product, each memory area
may be assigned to several slaves. Booting at the same address while using different AHB
slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that
performs remap action for every master independently.
0
X
X
X
X
X
X
X
X
X
X
-
-
-
Base Address
0x0000 0000
Slave
X
X
ARM
Data
-
926
1
X
X
X
X
X
X
X
X
X
X
-
-
-
summarizes the Slave Memory Mapping for each connected Master, depending on
Internal Memory Mapping
X
X
X
PDC
2
X
X
X
X
X
X
-
-
-
-
-
-
-
HOST
Internal ROM
OHCI
X
X
-
USB
BMS = 1
3
X
X
X
X
-
-
-
-
-
-
-
-
-
4 & 5
DMA
X
X
X
X
X
X
X
X
-
-
-
-
-
-
-
-
RCBx = 0
DMA
X
X
-
ISI
6
X
X
X
X
-
-
-
-
-
-
-
-
-
EBI NCS0
BMS
Master
DMA
LCD
X
X
-
7
X
X
-
-
-
-
-
-
-
-
-
-
-
= 0
et MAC
Ethern
X
X
-
8
X
X
X
X
-
-
-
-
-
-
-
-
-
Internal SRAM
Device
USB
RCBx = 1
HS
X
X
-
9
X
X
X
X
X
-
-
-
-
-
-
-
-
6355D–ATARM–7-Sep-11
EHCI
USB
Host
10
X
X
-
X
X
X
X
-
-
-
-
-
-
-
-
-
VDEC
X
11
-
-
X
X
-
-
-
-
-
-
-
-
-
-
-