SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 252

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.5.4.4
252
252
SAM9M10
SAM9M10
Reset Mode
The reset mode is a feature of the DDR2-SDRAM. This mode is activated by setting the low-
power command bits (LPCB) to 11 and the clock frozen command bit (CLK_FR) to 1.
When this mode is enabled, the DDRSDRC leaves normal mode (mode == 000) and the control-
ler is frozen. Before enabling this mode, the end user must assume there is not an access in
progress.
To exit reset mode, the low-power command bits (LPCB) must be set to “00”, clock frozen com-
mand bit (CLK_FR) set to 0 and an initialization sequence must be generated by software. See
Section 22.4.3 “DDR2-SDRAM Initialization” on page
234.
6355D–ATARM–7-Sep-11
6355D–ATARM–7-Sep-11