SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 254

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 22-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
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254
COMMAND
DQS[1:0]
BA[1:0]
DM1:0]
D[15:0]
A[12:0]
SDClK
SAM9M10
SAM9M10
NOP
0
3
READ
1
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from differ-
ent masters to the SDRAM device in a round-robin manner. If two or more master requests arise
at the same time, the master with the lowest number is serviced first, then the others are ser-
viced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput
for the SDRAM device, arbitration may only take place during the following cycles:
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For
4. Anticipated Access: When an anticipate read access is done while current access is
Anticipate command, Precharge/Active Bank 2
bursts of defined length, predicted end of burst matches the size of the transfer. For
bursts of undefined length, predicted end of burst is generated at the end of each four
beat boundary inside the INCR transfer.
not complete, the arbitration scheme can be changed if the anticipated access is not
the next access serviced by the arbitration scheme.
PRECH
Read access in Bank 1
2
Trp
NOP
Da
Db
ACT
Dc
Dd
READ
1
De
Df
Dg
Dh
NOP
Di
6355D–ATARM–7-Sep-11
6355D–ATARM–7-Sep-11
Dj
Dk
Dl