SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1152

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.5
Table 46-9.
1152
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
0x0018
0x001C
0x0020
0x0024
0x0028
0x002C
0x0030
0x0034
0x0038
0x003C
0x0040
0x0044
Offset
Video Decoder (VDEC) User Interface
SAM9M10
Register
ID Register
Decoder Interrupt Register
Decoder Device Configuration Register
Decoder Control Register 0
Decoder Control Register 1
Decoder Control Register 2
Decoder Control Register 3
Decoder Control Register 4
Decoder Control Register 5
Decoder Control Register 6
Base Address for Differential Motion Vector
Decoder Control Register 7
Decoded Picture Base Address
Reference Picture Index 0 Base Address
Reference Picture Index 1 Base Address
Reference Picture Index 2 Base Address
Reference Picture Index 3 Base Address
RLC/VLC Data Base Address
Video Decoder Register Mapping (All Decoders)
The VDEC User interface is split into two interfaces.
Table 46-8.
Note:
Decoder Mode
H264
MPEG4
H263
JPEG
VC1
MPEG2
MPEG1
• One that concerns Post Processor and is common to all Decoder Modes, described by Video
• One in which registers and fields depend on the Decoder Mode used. For best readability this
Post Processor Register Mapping.
document describes one Register Mapping for each Decoder Mode. The relations are given
in
Table
The decoder mode is defined by the field DEC_MODE in Decoder Control Register 0.
46-8.
Register Mapping vs. Decoder Mode
Refer to the following Register Mapping
Video Decoder Register Mapping (H264)
Video Decoder Register Mapping (MPEG4H263)
Video Decoder Register Mapping (MPEG4H263)
Video Decoder Register Mapping (JPEG)
Video Decoder Register Mapping (VC1)
Video Decoder Register Mapping (MPEG2MPEG1)
Video Decoder Register Mapping (MPEG2MPEG1)
(1)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(2)
X
X
X
X
X
X
X
–
X
X
X
X
X
X
X
X
X
–
(3)
X
X
X
X
X
X
X
–
–
–
–
–
X
X
X
X
X
X
(4)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(5)
X
X
X
X
X
X
X
–
–
–
–
–
X
X
X
X
X
X
VDEC_CTLR4
VDEC_CTLR5
VDEC_CTLR6
VDEC_CTLR7
Name
VDEC_IDR
VDEC_DIR
VDEC_DDCR
VDEC_CTLR0
VDEC_CTLR1
VDEC_CTLR2
VDEC_CTLR3
VDEC_DMVBA
VDEC_RLCVLCBA
VDEC_PICTBA
VDEC_PIDXBA0
VDEC_PIDXBA1
VDEC_PIDXBA2
VDEC_PIDXBA3
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
Access
6355D–ATARM–7-Sep-11
0x81701000
0x00000000
0x00000000
0x00000000
0x00000400
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset