SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 885

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 39-3.
Table 39-4.
Table 39-5.
39.4.3
6355D–ATARM–7-Sep-11
RGB 5:6:5
Mode
RGB 5:6:5
Mode
RGB 8:8:8
RGB 5:6:5
Clocks
RGB Format in Default Mode, RGB_CFG = 00, No Swap
RGB Format, RGB_CFG = 10 (Mode 2), No Swap
RGB Format in Default Mode, RGB_CFG = 00, Swap Activated
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
The RGB 5:6:5 input format is processed to be displayed as RGB 5:6:5 format, compliant with
the 16-bit mode of the LCD controller.
The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Manage-
ment Controller (APMC) through a Programmable Clock output or by an external oscillator
connected to the sensor.
None of the sensors embed a power management controller, so providing the clock by the
APMC is a simple and efficient way to control power consumption of the system.
Care must be taken when programming the system clock. The ISI has two clock domains, the
system bus clock and the pixel clock provided by sensor. The two clock domains are not syn-
chronized, but the system clock must be faster than pixel clock.
R4(i)
G2(i)
R4(i+1)
G2(i+1)
D7
G2(i)
B4(i)
G2(i+1)
B4(i+1)
D7
R0(i)
G0(i)
B0(i)
R0(i+1)
G3(i)
B0(i)
G3(i+1)
B0(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
D6
G1(i)
B3(i)
G1(i+1)
B3(i+1)
D6
R1(i)
G1(i)
B1(i)
R1(i+1)
G4(i)
B1(i)
G4(i+1)
B1(i+1)
R2(i)
R2(i+1)
G0(i)
G0(i+1)
D5
G0(i)
B2(i)
G0(i+1)
B2(i+1)
D5
R2(i)
G2(i)
B2(i)
R2(i+1)
G5(i)
B2(i)
G5(i+1)
B2(i+1)
R1(i)
R1(i+1)
B4(i)
B4(i+1)
D4
R4(i)
B1(i)
R4(i+1)
B1(i+1)
D4
R3(i)
G3(i)
B3(i)
R3(i+1)
R0(i)
B3(i)
R0(i+1)
B3(i+1)
R0(i)
B3(i)
R0(i+1)
B3(i+1)
D3
R3(i)
B0(i)
R3(i+1)
B0(i+1)
D3
R4(i)
G4(i)
B4(i)
R4(i+1)
R1(i)
B4(i)
R1(i+1)
B4(i+1)
G5(i)
G5(i+1)
B2(i)
B2(i+1)
D2
R2(i)
G5(i)
R2(i+1)
G5(i+1)
D2
R5(i)
G5(i)
B5(i)
R5(i+1)
R2(i)
G0(i)
R2(i+1)
G0(i+1)
G4(i)
B1(i)
G4(i+1)
B1(i+1)
D1
R1(i)
G4(i)
R1(i+1)
G4(i+1)
D1
R6(i)
G6(i)
B6(i)
R6(i+1)
R3(i)
G1(i)
R3(i+1)
G1(i+1)
SAM9M10
G3(i)
B0(i)
G3(i+1)
B0(i+1)
R0(i)
R0(i+1)
G3(i+1)
G7(i)
R4(i)
R4(i+1)
G2(i+1)
D0
G3(i)
D0
R7(i)
B7(i)
R7(i+1)
G2(i)
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