SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 816

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Table 38-3.
Notes:
38.5.4
Figure 38-4. Control Read and Write Sequences
38.5.5
816
CONTROL
(bidirectional)
OUT
(host toward device)
1. Control transfer must use endpoints with one bank and can be aborted using a stall handshake.
2. Isochronous transfers must use endpoints configured with two or three banks.
SAM9M10
USB V2.0 High Speed BUS Transactions
Endpoint Configuration
USB Transfer Events (Continued)
Control Write
Control Read
No Data
Control
Control Transfers
Bulk OUT Transfer
Interrupt OUT Transfer
Isochronous OUT Transfer
An endpoint handles all transactions related to the type of transfer for which it has been
configured.
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
A status IN or OUT transaction is identical to a data IN or OUT transaction.
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be
enabled when the End Of Reset interrupt occurs.
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
(1)
(2)
Status Stage
Status IN TX
Data OUT TX
Data IN TX
• Setup transaction
• Setup transaction
• Setup transaction
• Data OUT transaction
• Data OUT transaction
• Data OUT transaction
Data Stage
Data Stage
Data OUT TX
Data IN TX
Data IN transactions Status OUT transaction
Data OUT transactions Status IN transaction
Status IN transaction
Data OUT transaction
Data OUT transaction
Data OUT transaction
Status OUT TX
Status Stage
Status Stage
Status IN TX
6355D–ATARM–7-Sep-11