SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 259

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.8
The User Interface is connected to the APB bus.
The DDRSDRC is programmed using the registers listed in
Table 22-8.
6355D–ATARM–7-Sep-11
6355D–ATARM–7-Sep-11
Offset
0x00
0x60-0xE0
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C
0x20
0x24
0x2C
0x40
0x44
0x48
0x4C
0x50
0x54-0x58
0xE4
0xE8
DDR SDR SDRAM Controller (DDRSDRC) User Interface
Register Mapping
Register
DDRSDRC Mode Register
DDRSDRC Refresh Timer Register
DDRSDRC Configuration Register
DDRSDRC Timing Parameter 0 Register
DDRSDRC Timing Parameter 1 Register
DDRSDRC Timing Parameter 2 Register
Reserved
DDRSDRC Low-power Register
DDRSDRC Memory Device Register
DDRSDRC DLL Information Register
DDRSDRC High Speed Register
DDRSDRC Delay I/O Register
DDRSDRC Delay I/O Register
DDRSDRC Delay I/O Register
DDRSDRC Delay I/O Register
Reserved
Reserved
Reserved
DDRSDRC Write Protect Mode Register
DDRSDRC Write Protect Status Register
Name
DDRSDRC_MR
DDRSDRC_RTR
DDRSDRC_CR
DDRSDRC_TPR0
DDRSDRC_TPR1
DDRSDRC_TPR2
–
DDRSDRC_LPR
DDRSDRC_MD
DDRSDRC_DLL
DDRSDRC_HS
DDRSDRC_DELAY1
DDRSDRC_DELAY2
DDRSDRC_DELAY3
DDRSDRC_DELAY4
–
-
–
DDRSDRC_WPMR
DDRSDRC_WPSR
Table 22-8
Access
Read-write
Read-write
Read-write
Read-write
Read-write
Read-write
–
Read-write
Read-write
Read-only
Read-write
Read-write
Read-write
Read-write
Read-write
–
-
–
Read-write
Read-only
SAM9M10
SAM9M10
Reset
0x00000000
0x00000000
0x7024
0x20227225
0x3c80808
0x2062
–
0x10000
0x10
0x00000001
0x0
0x00000000
0x00000000
0x00000000
0x00000000
–
-
–
0x00000000
0x00000000
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