SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 246

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 22-15. Burst Read Access, Latency = 3, DDR2-SDRAM Devices
Figure 22-16. Burst Read Access, Latency = 2, SDR-SDRAM Devices
22.5.3
22.5.4
22.5.4.1
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246
COMMAND
COMMAND
DQS[1:0]
DQS[1:0]
DM[3:0]
SDCLK
BA[1:0]
DM[1:0]
D[31:0]
A[12:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
SAM9M10
SAM9M10
Refresh (Auto-refresh Command)
Power Management
Self Refresh Mode
NOP
0
NOP
0
3
col a
READ
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated
internally by the SDRAM device and incremented after each auto-refresh automatically. The
DDRSDRC generates these auto-refresh commands periodically. A timer is loaded with the
value in the register DDRSDRC_TR that indicates the number of clock cycles between refresh
cycles. When the DDRSDRC initiates a refresh of an SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM device, the slave indicates that
the device is busy. A request of refresh does not interrupt a burst transfer in progress.
This mode is activated by setting low-power command bits [LPCB] to ‘01’ in the
DDRSDRC_LPR Register
Col a
READ
F
Latency = 2
NOP
Latency = 3
NOP
DaDb
DcDd
Da
DeDf
Db
BST
Dc
Dd
Dg Dh
De
NOP
Df
Dg
6355D–ATARM–7-Sep-11
6355D–ATARM–7-Sep-11
Dh