SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1385

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6355D–ATARM–7-Sep-11
Doc. Rev
6355B
6355A
Comments
Bus Matrix
“12-layer” Matrix instead of “11-layer” in
DDRSDRC
In
- TRTP bitfield reset value (0 --> 2) changed.
- 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”.
- TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed.
In
In
Electrical Characteristics
-
- Figure below
- Ultra low power Mode value changed in
-
ERRATA
-
-
-
-
- 3
parity”
External Memories
- DQM0-DQM3 added to
-
-
- On
LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
Mechanical Characteristics
- New
PMC
- Note added to
Register”.
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the
USART
- LIN Mode condition now shown in
Transmitter
VDEC
- DivX line removed from
First issue
Section 47.14 “DDRSDRC Timings”
Section 47.15.1.1 “Maximum SPI Frequency”
“Boot ROM”
“Static Memory Controller (SMC)”
“Touch Screen (TSADCC)”
“USB High Speed Host Port (UHPHS) and Device Port (UDPHS)”
Table
Section 20. “External Memories”
Section 22.7.6 “DDRSDRC Timing 2 Parameter
Section 22.7.7 “DDRSDRC Low-power
Section 22.4.4.1 “Self Refresh
“Error Corrected Code Controller (ECC)”
Figure 6-1 “SAM9M10 Memory
Figure 48-1 “324-ball TFBGA Package Drawing”
,
20-5, row ‘A15’ edited.
“Unsupported ECC per 512 words”
(USART)”.
errata added.
Table 47-7, “Main Oscillator Characteristics,” on page 1341
Section 26.3 “Master Clock Controller”
Figure 20-4 “EBI Connections to Memory
Section 46. “Video Decoder (VDEC)”
errata added.
Mode”, UDP_EN bitfield replaced by UPD_MR.
reorganized.
Section 31. “Universal Synchronous Asynchronous Receiver
errata added.
Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2-
edited.
Table 47-3, “Power Consumption for Different Modes”
Register”, UPD_MR bitfield added to the table at [21:20].
and
errata added:
Section 19. “Bus Matrix (MATRIX)”
added.
“Unsupported hardware ECC on 16-bit Nand Flash”
Register”,
“SAM9M10 Errata - Rev. A Parts”
and
and Max. weight changed in
“Uncomplete parity status when error in ECC
Section 26.11.12 “PMC Master Clock
Devices”.
errata added.
Table edited.
Table 48-2
Table.
SAM9M10
Change
Request
Ref.
7171
7146
6786
7089
7134- 7193
7063
7195
7173
7148
6977
7165
7194
7192
7123
7027
6946
6954
7106
rfo
6944
6976
1385