SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 749

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

35.13.17 HSMCI Configuration Register
Name:
Addresses:
Access:
• FIFOMODE: HSMCI Internal FIFO control mode
0 = A write transfer starts when a sufficient amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the HSMCI internal FIFO size, then the write transfer starts as soon
as half the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer
starts as soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is
written in the internal FIFO.
1 = A write transfer starts as soon as one data is written into the FIFO.
• FERRCTRL: Flow Error flag reset control mode
0 = When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag.
1 = When an underflow/overflow condition flag is set, a read status resets the flag.
• HSMODE: High Speed Mode
0 = Default bus timing mode.
1 = If set to one, the host controller outputs command line and data lines on the rising edge of the card clock. The Host
driver shall check the high speed support in the card registers.
• LSYNC: Synchronize on the last block
0 = The pending command is sent at the end of the current data block.
1 = The pending command is sent at the end of the block transfer when the transfer length is not infinite (block count shall
be different from zero).
6355D–ATARM–7-Sep-11
31
23
15
–
–
7
–
30
22
14
HSMCI_CFG
0xFFF80054 (0), 0xFFFD0054 (1)
Read-write
–
–
6
–
29
21
13
–
–
–
5
–
FERRCTRL
LSYNC
28
20
12
–
–
4
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
25
17
–
–
9
–
1
–
SAM9M10
FIFOMODE
HSMODE
24
16
–
–
8
0
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