SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1018

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

1018
SAM9M10
Figure 42-4. Non Overlapped Center Aligned Waveforms
Note:
• the waveform duty cycle. This channel parameter is defined in the CDTY field of the
• the waveform polarity. At the beginning of the period, the signal can be at high or low level.
• the waveform alignment. The output waveform can be left or center aligned. Center aligned
If the waveform is center aligned then the output waveform period depends on the counter
source clock and can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will
be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes,
respectively:
PWM_CDTYx register.
If the waveform is left aligned then:
If the waveform is center aligned, then:
This property is defined in the CPOL field of the PWM_CMRx register. By default the signal
starts by a low level.
waveforms can be used to generate non overlapped waveforms. This property is defined in
the CALG field of the PWM_CMRx register. The default mode is left aligned.
--------------------------------------------- -
------------------------------------------ -
--------------------------------------------------- -
PWM0
PWM1
X*CPRD*DIVA
2
2*X*CPRD*DIVA
duty cycle
duty cycle
X
1. See
MCK
MCK
MCK
CPRD
Figure 42-5 on page 1020
=
=
No overlap
----------------------------------------------------------------------------------------------------------- -
----------------------------------------------------------------------------------------------------------------------------- -
period 1
or
period
or
--------------------------------------------- -
X*CPRD*DIVB
Period
--------------------------------------------------- -
2*X*CPRD*DIVB
–
MCK
2
MCK
fchannel_x_clock
–
1
period
period
fchannel_x_clock
for a detailed description of center aligned waveforms.
2
CDTY
CDTY
6355D–ATARM–7-Sep-11