SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 78

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 12-8. Watchdog Reset
12.4.5
78
WDRPROC = 0
SAM9M10
Reset State Priorities
Only if
periph_nreset
proc_nreset
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
The Reset State Manager manages the following priorities between the different reset sources,
given in descending order:
Particular cases are listed below:
(nrst_out)
• If WDRPROC = 1, only the processor reset is asserted.
• Backup Reset
• Wake-up Reset
• Watchdog Reset
• Software Reset
• User Reset
• When in User Reset:
• When in Software Reset:
RSTTYP
wd_fault
NRST
SLCK
MCK
– A watchdog event is impossible because the Watchdog Timer is being reset by the
– A software reset is impossible, since the processor reset is being activated.
– A watchdog event has priority over the current state.
– The NRST has no effect.
proc_nreset signal.
Freq.
Any
Any
Processor Startup
= 3 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x2 = Watchdog Reset
6355D–ATARM–7-Sep-11