SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 696

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

35.6
35.6.1
35.6.2
35.6.3
696
Product Dependencies
SAM9M10
I/O Lines
Power Management
Interrupt
The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with
PIO lines. The programmer must first program the PIO controllers to assign the peripheral func-
tions to HSMCI pins.
Table 35-2.
The HSMCI is clocked through the Power Management Controller (PMC), so the programmer
must first configure the PMC to enable the HSMCI clock.
The HSMCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling the HSMCI interrupt requires programming the AIC before configuring the HSMCI.
Table 35-3.
Instance
HSMCI0
HSMCI1
Instance
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI0
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
HSMCI1
I/O Lines
Peripheral IDs
11
29
ID
MCI0_CDA
MCI1_CDA
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_DA4
MCI1_DA5
MCI1_DA6
MCI1_DA7
MCI0_CK
MCI1_CK
Signal
I/O Line
PA22
PA31
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA1
PA0
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
6355D–ATARM–7-Sep-11
Peripheral
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A