SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1305

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.11.2
Name:
Access:
• MAX_BURST_LEN: Maximum burst length for post-processor bus transactions
Valid values for AHB are 0, 1, 4, 8 and 16.
0: AHB INCR transfer type is used always.
1: AHB SINGLE transfer type is used always.
4, 8, 16: Set AHB maximum burst length to INCR4, INCR8 or INCR16. Also INCR and SINGLE types are allowed.
• PPO_LE: Post-processor Output Endian Mode (for Y Cb Cr)
0: Big endian
1: Little endian
For 16-bit RGB data, this bit woks as a pixel swapping bit.
• PPI_LE: Post-processor Input Endian Mode
0: Big endian
1: Little endian
• PPDCGE: Post-processor Dynamic Clock Gating Enable
0: Clock is running for all post-processor structures.
1: Clock is gated for post-processor structures that are not used.
Clock gating value should be changed only when the post-processor is disabled.
• AHB_BURST: AHB precise burst and data discard enable
0: INCR bursts of undefined length 2 or 3 may be issued when necessary.
1: Only the precise AHB bursts (SINGLE, INCR4, INCR8 and INCR16) are used in SDRAM read accesses. Extra data is
discarded internally.
• HLOCK: HLOCK enable
0: Locked transfers disabled.
1: Locked transfers enabled.
When a locked transfer is granted, bus grant cannot be lost even if a higher priority master requests the bus.
6355D–ATARM–7-Sep-11
HLOCK
PPI_LE
31
23
15
–
–
7
Post Processor Device Configuration Register
PPO_LE
30
22
14
VDEC_PPCR
Read-write
–
–
–
6
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
27
19
11
–
–
–
3
MAX_BURST_LEN
26
18
10
–
–
–
2
AHB_BURST
25
17
–
–
9
1
SAM9M10
PPDCGE
24
16
–
–
8
0
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