SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 369
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
SAM9M10
Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.SAM9261.pdf
(248 pages)
3.SAM9M10.pdf
(59 pages)
4.SAM9M10.pdf
(1398 pages)
Specifications of SAM9M10
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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26.11.13 PMC Programmable Clock Register
Name:
Address:
Access:
• CSS: Master Clock Selection
• PRES: Programmable Clock Prescaler
• SLCKMCK: Slow Clock or Master Clock Selection
0 = Slow clock is selected
1 = Master clock is selected
To select between Slow Clock and Master Clock, the CSS field must be programmed to ‘00’.
6355D–ATARM–7-Sep-11
31
23
15
–
–
–
7
–
PMC_PCKx
0xFFFFFC40
Read/Write
0
0
0
0
1
1
1
1
0
0
1
1
30
22
14
–
–
–
6
–
CSS
29
21
13
–
–
–
5
–
PRES
0
0
1
1
0
0
1
1
0
1
0
1
28
20
12
–
–
–
4
Clock Source Selection
Slow Clock or Master Clock may be selected depending on
SLCKMCK field.
Main Clock is selected.
PLLACK/PLLADIV2 is selected.
UPLLCK is selected.
PRES
27
19
11
–
–
–
3
0
1
0
1
0
1
0
1
26
18
10
–
–
–
2
Programmable Clock
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Reserved
25
17
–
–
–
9
1
SAM9M10
CSS
SLCKMCK
24
16
–
–
8
0
369
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