SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 765

• Manufacturer Part Number: SAM9M10
• Manufacturer: Atmel Corporation

Specifications of SAM9M10

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

36.4.13
6355D–ATARM–7-Sep-11
PHY Maintenance
An ARP request event is detected if all of the following are true:
The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame.
The reserved value of 0x0000 for the Wake-on-LAN target address value does not cause an
ARP request event, even if matched by the frame.
A specific address 1 filter match event occurs if all of the following are true:
A multicast filter match event occurs if all of the following are true:
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO
interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are config-
ured for the
The PHY maintenance register is implemented as a shift register. Writing to the register starts a
shift operation which is signalled as complete when bit two is set in the network status register
(about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the net-
work configuration register). An interrupt is generated as this bit is set. During this time, the MSB
of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of
management operation, the bits have shifted back to their original locations. For a read opera-
tion, the data bits are updated with data read from the PHY. It is important to write the correct
values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read
clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation,
see the network configuration register in the
•
• ARP request events are enabled through bit 17 of the Wake-on-LAN register
• broadcasts are allowed by bit 5 in the network configuration register
• the frame has a broadcast destination address (bytes 1 to 6)
• the frame has a type ID field of 0x0806 (bytes 13 and 14)
• the frame has an ARP operation field of 0x0001 (bytes 21 and 22)
•
•
•
•
•
• the frame’s destination address matches against the multicast hash filter
• the frame’s destination address is not a broadcast
there are 16 repetitions of the contents of specific address 1 register immediately
the synchronization
the least significant 16 bits of the frame’s ARP target protocol address (bytes 41
match the value programmed in bits[15:0] of the Wake-on-LAN register
specific address 1 events are enabled through bit 18 of the
the frame’s destination address matches the value programmed in the specific
registers
multicast hash events are enabled through bit 19 of the
multicast hash filtering is enabled through bit 6 of the network configuration
same speed and duplex configuration.
“Network Control Register” on page
Wake-on-LAN
Wake-on-LAN
register
SAM9M10
register
register
772.
address 1
and 42)
following
765