SAM9M10 Atmel Corporation, SAM9M10 Datasheet - Page 1254

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SAM9M10

Manufacturer Part Number
SAM9M10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9M10

Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
Yes
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No / Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
46.9.3
Name:
Address:
Access:
• MAX_BURST_LEN: Maximum Burst Length for Decoder Bus Transactions
Valid values for AHB are 0, 1, 4, 8, 16 and 17.
0: INCR transfer type is used always.
1: SINGLE transfer type is used always.
4: INCR4, INCR and SINGLE transfers are allowed. INCR used for 2 and 3 bursts.
8: INCR8, INCR4, INCR and SINGLE transfers are allowed. INCR used for 2 and 3 bursts.
16: INCR16, INCR8, INCR4, INCR and SINGLE transfers are allowed. INCR used for 2 and 3 bursts.
17: INCR16, INCR8, INCR4, INCR and SINGLE transfers are allowed. INCR used for 2, 3, 5, 6, 7, 9, 10, 11, 12, 13, 14 and
15 bursts.
• PRIOR: Decoder Core Internal Bus Service Priority
0: Dynamic priority depending on stream content.
1: Post-processor output write has highest priority.
2: Input stream read has highest priority.
3: Reference picture read has highest priority, then post-processor transactions.
4: Reference picture read has highest priority, then decoder output write.
• DO_LE: Decoder Output Endian Mode
0: Big endian
1: Little endian
• INTCE_LE: Interface Endian Mode
0: Big endian
1: Little endian
• DDCGE: Decoder Dynamic Clock Gating Enable
0: Clock is running for all structures.
1254
HTI
31
23
15
7
SAM9M10
Decoder Device Configuration Register
PRIOR
30
22
14
VDEC_DDCR
0x00900008
Read-write
6
LAT_COMP
DI_LE
29
21
13
5
28
20
12
4
27
19
11
3
MAX_BURST_LEN
AHB_BURST
DDCGE
26
18
10
2
INTCE_LE
DOPF
25
17
9
1
6355D–ATARM–7-Sep-11
LAT_COMP
DO_LE
24
16
8
0

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