LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 993
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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42.4.6.10 Output stage 3 to 19 control registers
Table 943. Output stage 1 control register (OUTCLK_1_CTRL, address 0x4005 004C) bit
These registers control base clocks 2 to 19.
Table 944. Output stage 3 to 19 control registers (OUTCLK_2_CTRL to OUTCLK_19_CTRL,
Bit
0
10:1
11
23:12
27:24
31:28
Bit
0
10:1
11
23:12
Symbol
PD
-
AUTOBLOCK
-
CLK_SEL
-
Symbol
PD
-
AUTOBLOCK
-
description
address 0x4005 0050 to 0x4005 0094) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Value
0
1
0
1
0x00
0x07
Value
0
1
0
1
Description
Output stage power down
Output stage enabled (default)
power-down
Reserved
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Clock-source selection.
Reserved
PLL0 (default)
Reserved
Description
Output stage power down
Output stage enabled (default)
power-down
Reserved
Block clock automatically during frequency
change
Autoblocking disabled
Autoblocking enabled
Reserved
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
-
0
-
Reset
value
0
-
0
-
0x07
-
993 of 1164
Access
R/W
-
R/W
-
Access
R/W
-
R/W
-
R/W
-
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