LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 271
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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16.6.7 DMA Raw Error Interrupt Status Register
16.6.8 DMA Enabled Channel Register
16.6.9 DMA Software Burst Request Register
The RAWINTERRSTAT Register is read-only and indicates which DMA channel is
requesting an error interrupt prior to masking. (Note: the IntErrStat Register contains the
same information after masking.) A HIGH bit indicates that the error interrupt request is
active prior to masking.
Table 203. DMA Raw Error Interrupt Status Register (RAWINTERRSTAT, address 0x4000
The ENBLDCHNS Register is read-only and indicates which DMA channels are enabled,
as indicated by the Enable bit in the CCONFIG Register. A HIGH bit indicates that a DMA
channel is enabled. A bit is cleared on completion of the DMA transfer.
Table 204. DMA Enabled Channel Register (ENBLDCHNS, address 0x4000 201C) bit
The SOFTBREQ Register is read/write and enables DMA burst requests to be generated
by software. A DMA request can be generated for each source by writing a 1 to the
corresponding register bit. A register bit is cleared when the transaction has completed.
Reading the register indicates which sources are requesting DMA burst transfers. A
request can be generated from either a peripheral or the software request register. Each
bit is cleared when the related transaction has completed.
Bit
7:0
31:8
Bit
7:0
31:8
Symbol
RAWINTERRSTAT Status of the error interrupt for DMA channels prior
-
Symbol
ENABLEDCHANNELS Enable status for DMA channels. Each bit
-
2018) bit description
description
All information provided in this document is subject to legal disclaimers.
Chapter 16: LPC18xx General Purpose DMA (GPDMA) controller
Rev. 00.13 — 20 July 2011
Description
to masking. Each bit represents one channel:
0 - the corresponding channel has no active error
interrupt request.
1 - the corresponding channel does have an active
error interrupt request.
Reserved. Read undefined.
Description
represents one channel:
0 - DMA channel is disabled.
1 - DMA channel is enabled.
Reserved. Read undefined.
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
-
Reset
value
0x00
-
271 of 1164
Access
RO
-
-
Access
RO
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