LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1040
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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User manual
42.7.3.1 Digital pin function
42.7.3.2 Digital pin mode
42.7.3.3 I
42.7.3.4 USB1 DP1/DM1 pins
42.7.3.5 EMC signal delay control
42.7.3 General description
Table 964. SCU clocking and power control
The system control unit determines the function and electrical mode of the digital pins. By
default function 0 is selected for all pins with pull-up enabled.
Remark: Analog I/Os for the ADCs and the DAC as well as several USB functions reside
on separate pins and are not controlled through the SCU.
The FUNC bits in the SFSX_Y registers control the function of each pin. If the function is
GPIO, the GPIOnDIR registers determine whether the pin is configured as an input or
output (see
automatically depending on the pin’s functionality. The GPIOnDIR registers have no effect
for peripheral functions.
The MODE bits in the SFSX_Y registers allow the selection of on-chip pull-up or pull-down
resistors for each pin or select the repeater mode.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no
pull-up/pull-down. The default value is pull-up enabled.
The repeater mode enables the pull-up resistor if the pin is at a logic HIGH and enables
the pull-down resistor if the pin is at a logic LOW. This causes the pin to retain its last
known state if it is configured as an input and is not driven externally. Repeater mode may
typically be used to prevent a pin from floating (and potentially using significant power if it
floats to an indeterminate state) if it is temporarily not driven.
The EHS bits of the SFSI2C0 register
<tbd>
The SCU contains a programmable delay control for all EMC input and output data,
address, and control signals. For detail on use of the EMC delay modes, see
Clock to SCU register interface
2
•
•
C0-bus pins
Standard mode/Fast-mode I
I
Fast-mode Plus and High-speed mode with input glitch filter (this includes an
open-drain output according to the I
2
C-bus specification).
Table
All information provided in this document is subject to legal disclaimers.
280). For any peripheral function, the pin direction is controlled
Rev. 00.13 — 20 July 2011
2
C (this includes an open-drain output according to the
Base clock
BASE_M3_CLK
(Table
2
C-bus specification).
968) configure different I
Branch clock
CLK_M3_SCU
Chapter 42: Appendix
2
UM10430
C-modes:
© NXP B.V. 2011. All rights reserved.
Table
Maximum
frequency
150 MHz
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