LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 913
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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NXP Semiconductors
40.5 Boot process flowchart
<Document ID>
User manual
Fig 148. Boot process flowchart
(1) For details on handling the crystal frequency, see
(2) For details on available ISP commands based on the CRP settings see
CRP1/2/3 ENABLED?
USER CODE VALID?
CRP3 ENABLED?
WATCHDOG
FLAG SET?
INITIALIZE
RESET
A
yes
yes
yes
no
no
yes
no
no
All information provided in this document is subject to legal disclaimers.
no
RECEIVE CRYSTAL
RUN AUTO-BAUD
Rev. 00.13 — 20 July 2011
SUCCESSFUL?
FREQUENCY
(P2_7=LOW)
AUTO-BAUD
Enter ISP
MODE?
ENABLE DEBUG
Section 40.9.9 “Re-invoke ISP” on page 930
yes
yes
1
Chapter 40: LPC18xx flash programming interface
no
Section 40.7 “Code Read Protection (CRP)”
USER CODE
VALID?
RUN ISP COMMAND
HANDLER
EXECUTE INTERNAL
2
yes
USER CODE
A
UM10430
© NXP B.V. 2011. All rights reserved.
913 of 1164
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