LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 1134
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 607. RI Compare Value register (COMPVAL - address
Table 608. RI Mask register (MASK - address 0x400C 0004)
Table 609. RI Control register (CTRL - address 0x400C
Table 610. RI Counter register (COUNTER - address
Table 611. Alarm timer clocking and power control . . . . .688
Table 612. Register overview: Alarm timer (base address
Table 613. Downcounter register (DOWNCOUNTER -
Table 614. Preset value register (PRESET - 0x4004 0004) bit
Table 615. Interrupt clear enable register (CLR_EN - 0x4004
Table 616. Interrupt set enable register (SET_EN - 0x4004
Table 617. Interrupt status register (STATUS - 0x4004 0FE0)
Table 618. Interrupt enable register (ENABLE - 0x4004
Table 619. Interrupt clear status register (CLR_STAT -
Table 620. Interrupt set status register (SET_STAT - 0x4004
Table 621. WWDT clocking and power control . . . . . . . .691
Table 622. Register overview: Watchdog timer (base
Table 623. Watchdog Mode register (MOD - 0x4008 0000)
Table 624. Watchdog operating modes selection . . . . . .695
Table 625. Watchdog Timer Constant register (TC - 0x4008
Table 626. Watchdog Feed register (FEED - 0x4008 0008)
Table 627. Watchdog Timer Value register (TV - 0x4008
Table 628. Watchdog Timer Warning Interrupt register
Table 629. Watchdog Timer Window register (WINDOW -
Table 630. RTC clocking and power control . . . . . . . . . .699
Table 631. RTC pin description . . . . . . . . . . . . . . . . . . . .700
Table 632. Register overview: RTC (base address 0x4004
Table 633. Register overview: REGFILE (base address
Table 634. Interrupt Location Register (ILR - address
Table 635. Clock Control Register (CCR - address
Table 636. Counter Increment Interrupt Register (CIIR -
Table 637. Alarm Mask Register (AMR - address
Table 638. Consolidated Time register 0 (CTIME0 - address
<Document ID>
User manual
0x400C 0000) bit description . . . . . . . . . . . . .685
bit description . . . . . . . . . . . . . . . . . . . . . . . . .685
0008) bit description . . . . . . . . . . . . . . . . . . . .685
0x400C 000C) bit description . . . . . . . . . . . . .686
0x4004 0000) . . . . . . . . . . . . . . . . . . . . . . . . .689
0x4004 0000) bit description . . . . . . . . . . . . .689
description . . . . . . . . . . . . . . . . . . . . . . . . . . .689
0FD8) bit description . . . . . . . . . . . . . . . . . . .689
0FDC) bit description . . . . . . . . . . . . . . . . . . .690
bit description . . . . . . . . . . . . . . . . . . . . . . . . .690
0FE4) bit description. . . . . . . . . . . . . . . . . . . .690
0x4004 0FE8) bit description . . . . . . . . . . . . .690
0FEC) bit description . . . . . . . . . . . . . . . . . . .690
address 0x4008 0000) . . . . . . . . . . . . . . . . . .693
bit description . . . . . . . . . . . . . . . . . . . . . . . . .694
0004) bit description . . . . . . . . . . . . . . . . . . . .695
bit description . . . . . . . . . . . . . . . . . . . . . . . . .696
000C) bit description. . . . . . . . . . . . . . . . . . . .696
(WARNINT - 0x4008 0014) bit description . . .696
0x4008 0018) bit description . . . . . . . . . . . . .697
6000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .701
0x4004 1000) . . . . . . . . . . . . . . . . . . . . . . . . .701
0x4004 6000) bit description . . . . . . . . . . . . .702
0x4004 6008) bit description . . . . . . . . . . . . .702
address 0x4004 600C) bit description . . . . . .703
0x4004 6010) bit description . . . . . . . . . . . . .703
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 639. Consolidated Time register 1 (CTIME1 - address
Table 640. Consolidated Time register 2 (CTIME2 - address
Table 641. Time Counter relationships and values . . . . . 705
Table 642. Time Counter registers . . . . . . . . . . . . . . . . . 705
Table 643. Second register (SEC - address 0x4004 6020) bit
Table 644. Minute register (MIN - address 0x4004 6024) bit
Table 645. Hour register (HRS - address 0x4004 6028) bit
Table 646. Days of month register (DOM - address
Table 647. Days of week register (DOW - address
Table 648. Days of year register (DOY - address
Table 649. Month register (MONTH - address 0x4004 6038)
Table 650. Year register (YEAR - address 0x4004 603C) bit
Table 651. Calibration register (CALIBRATION - address
Table 652. Alarm registers . . . . . . . . . . . . . . . . . . . . . . . 708
Table 653. Alarm Second register (ASEC - address
Table 654. Alarm Minute register (AMIN - address
Table 655. Alarm Hour register (AHRS - address
Table 656. Alarm Days of month register (ADOM - address
Table 657. Alarm Days of week register (ADOW - address
Table 658. Alarm Days of year register (ADOY - address
Table 659. Alarm Month register (AMON - address
Table 660. Alarm Year register (AYRS - address
Table 661. USART0/2/3 clocking and power control. . . . 712
Table 662. USART0/2/3 pin description . . . . . . . . . . . . . 713
Table 663. Register overview: UART0/2/3 (base address:
Table 664. UART Receiver Buffer Registers when DLAB = 0,
Table 665. UART Transmitter Holding Register when
Table 666. UART Divisor Latch LSB Register when
0x4004 6014) bit description . . . . . . . . . . . . . 704
0x4004 6018) bit description . . . . . . . . . . . . . 704
0x4004 601C) bit description . . . . . . . . . . . . . 705
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
0x4004 602C) bit description . . . . . . . . . . . . . 706
0x4004 6030) bit description . . . . . . . . . . . . . 706
0x4004 6034) bit description . . . . . . . . . . . . . 707
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 707
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
0x4004 6040) bit description . . . . . . . . . . . . . 707
0x4004 6060) bit description . . . . . . . . . . . . . 708
0x4004 6064) bit description . . . . . . . . . . . . . 708
0x4004 6068) bit description . . . . . . . . . . . . . 709
0x4004 606C) bit description . . . . . . . . . . . . . 709
0x4004 6070) bit description . . . . . . . . . . . . . 709
0x4004 6074) bit description . . . . . . . . . . . . . 709
0x4004 6078) bit description . . . . . . . . . . . . . 709
0x4004 607C) bit description . . . . . . . . . . . . . 710
0x4008 1000, 0x400C 1000, 0x400C 2000) . 713
Read Only (RBR - addresses 0x4008 1000
(UART0), 0x400C 1000 (UART2), 0x400C 2000
(UART3)) bit description . . . . . . . . . . . . . . . . 715
DLAB = 0, Write Only(THR - addresses
0x4008 1000 (UART0), 0x400C 1000 (UART2),
0x400C 2000 (UART3)) bit description . . . . . 715
DLAB = 1 (DLL - addresses 0x4008 1000
(UART0), 0x400C 1000 (UART2), 0x400C 2000
(UART3)) bit description. . . . . . . . . . . . . . . . . 716
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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