LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 467
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 389. Port Status and Control register in host mode (PORTSC1_H - address 0x4000 7184) bit description
<Document ID>
User manual
Bit
12
13
15:14 PIC1_0
19:16 PTC3_0
20
Symbol
PP
-
WKCN
…continued
Value Description
-
0
1
-
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0
1
Port power control
Reserved
Port indicator control
Port indicators are off.
Undefined
Port test control
J_STATE
K_STATE
Wake on connect enable (WKCNNT_E)
Host controller requires port power control switches. This bit represents the
current setting of the switch (0=off, 1=on). When power is not available on
a port (i.e. PP equals a 0), the port is non-functional and will not report
attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is
a one, the PP bit in each affected port may be transitioned by the host
controller driver from a one to a zero (removing power from the port).
Port power off.
Port power on.
Writing to this field controls the value of the pins USB1_IND1 and
USB1_IND0.
Amber
Green
Any value other than 0000 indicates that the port is operating in test mode.
The FORCE_ENABLE_FS and FORCE ENABLE_LS are extensions to the
test mode support specified in the EHCI specification. Writing the PTC field
to any of the FORCE_ENABLE_{HS/FS/LS} values will force the port into
the connected and enabled state at the selected speed. Writing the PTC
field back to TEST_MODE_DISABLE will allow the port state machines to
progress normally from that point. Values 0x8 to 0xF are reserved.
TEST_MODE_DISABLE
SE0 (host)/NAK (device)
Packet
FORCE_ENABLE_HS
FORCE_ENABLE_FS
FORCE_ENABLE_LS
This bit is 0 if PP (Port Power bit) is 0
Disables the port to wake up on device connects.
Writing this bit to a one enables the port to be sensitive to device connects
as wake-up events.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
Reset
value
0
0
00
0000
0
© NXP B.V. 2011. All rights reserved.
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