LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 111
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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11.1 How to read this chapter
11.2 Basic configuration
11.3 General description
<Document ID>
User manual
Fig 21. RGU Block diagram
WWDT reset
BOD reset
RESET
RGU
The C_CAN1 reset (#54) is available on parts LPC1850_30_20_10 Rev ‘A’ only.
Table 88.
The RGU is reset by a BUS_RST (reset #8).
Remark: Support for the ARM Cortex-M3 SYSRESETREQ is not implemented on the
LPC18xx.
The RGU allows generation of independent reset signals for various blocks and
peripherals on the LPC18xx. Each reset signal is asserted by a reset generator with one
output (the reset signal) and one or more inputs, which link the reset generators together
and create a reset hierarchy.
RGU
RGU delay clocks
GENERATOR
CORE_RST
UM10430
Chapter 11: LPC18xx Reset Generation Unit (RGU)
Rev. 00.13 — 20 July 2011
RGU clocking and power control
All information provided in this document is subject to legal disclaimers.
PERIPH_RST
GENERATOR
Base clock
BASE_M3_CLK
BASE_SAFE_CLK
Rev. 00.13 — 20 July 2011
MASTER_RST
GENERATOR
24
7
Branch clock
CLK_M3_BUS
-
Bus bridges,
memory controllers
APB peripherals, GPIO
Cortex-M3 core
AHB peripherals (USB0/1, LCD,
Ethernet, GPDMA, SDIO, AES)
WWDT
CREG; RTC domain peripherals; PMC
© NXP B.V. 2011. All rights reserved.
Maximum
frequency
150 MHz
12 MHz
User manual
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