LPC1810FET100,551 NXP Semiconductors, LPC1810FET100,551 Datasheet - Page 907
LPC1810FET100,551
Manufacturer Part Number
LPC1810FET100,551
Description
IC MCU 32BIT 136KB FLSH 100TFBGA
Manufacturer
NXP Semiconductors
Series
LPC18xxr
Datasheets
1.LPC1830FET256551.pdf
(87 pages)
2.LPC1810FET100551.pdf
(2 pages)
3.LPC1810FET100551.pdf
(1164 pages)
Specifications of LPC1810FET100,551
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
150MHz
Connectivity
CAN, EBI/EMI, I²C, Microwire, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
Number Of I /o
64
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
136K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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39.5 Register description
<Document ID>
User manual
39.5.1 D/A converter register
39.5.2 D/A Converter Control register
Table 836. Register overview: DAC (base address 0x400E 1000)
This read/write register includes the digital value to be converted to an analog output
value and a bit that trades off performance vs. power.
Table 837: D/A Converter register (CR - address 0x400E 1000) bit description
This read/write register enables the DMA operation and controls the DMA timer.
Table 838. D/A Control register (CTRL - address 0x400E 1004) bit description
Name
CR
CTRL
CNTVAL
Bit
5:0
15:6
16
31:17 -
Bit
0
1
Symbol
INT_DMA_REQ
DBLBUF_ENA
Symbol Value
-
VALUE
BIAS
All information provided in this document is subject to legal disclaimers.
0
1
R/W
Access
R/W
R/W
Rev. 00.13 — 20 July 2011
Value Description
0
1
0
1
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
After the selected settling time after this field is written with a
new VALUE, the voltage on the DACOUT pin (with respect to
V
Settling time
The settling time of the DAC is 1 s max, and the maximum
current is 700 A.
The settling time of the DAC is 2.5 s and the maximum
current is 350 A.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
SSA
) is VALUE/1024 VDDA.
DMA request
This bit is cleared on any write to the DACR register.
This bit is set by hardware when the timer times out.
DMA double-buffering
DACR double-buffering is disabled.
When this bit and the CNT_ENA bit are both set, the
double-buffering feature in the DACR register will be
enabled. Writes to the DACR register are written to a
pre-buffer and then transferred to the DACR on the next
time-out of the counter.
Address
offset
0x000
0x004
0x008
Description
DAC register. Holds the conversion
data.
DAC control register.
DAC counter value register.
Chapter 39: LPC18xx DAC
UM10430
© NXP B.V. 2011. All rights reserved.
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